x 86-64 téraoctets de mémoire virtuelle Comment ? -Débordement de pile

Intel x86 memory model has segmentation and paging. What does it mean that the system can address upto 64 terabytes of virtual memory. My understanding is that only 4GB of virtual memory is addressable. What is the gap here? This is all in the context of 32 bit processor

Here is the math:

2^13 (segments selectors) * 2 (LDT or GDT) * 2^32 = 2^46 = 64 Terabytes. This is referred to in the literature as total virtual memory. Are they wrongly terming it virtual memory? What confuses me is, the processor itself has only 32 bit address lines.

Or, are they trying to say that this is the total virtual memory that can be allocated total (across all processes?)

I think what is being said here that the x86 processor is capable of addressing up to that much memory, not that it does in practice. That would only be possible if the program used the segmented memory model and utilized both a full segment and GP register and the CPU's were wired use them in that way. However, programs today typically use the flat memory model (which can address less memory) and operating systems does not support addressing that much memory AFAIK.

And from §3.3.1 of the manual [1]:

Segmented memory model — [...] Programs running on an IA-32 processor can address up to 16,383 [2¹⁴] segments of different sizes and types, and each segment can be as large as 2³² bytes.

So apparently they are wired to be able to address 2⁴⁶ (64 TiB) bytes of (virtual and physical?) memory but we are confined to what memory model is used in the programs and whether the operating system supports it.

It would actually be usable – you can swap memory to disk and actually address that much virtual memory if need be, so the figures should be correct, and you can call it virtual memory indeed.

However, an x86 processor in 32 bit mode would only be able to address 4 GB at once without swapping, and no system I've heard of ever used that much memory while in 32-bit mode, and it would usually not be very practical due to performance.

1) the segment descriptor is chosen out of these 2^13*2=2^14 by a segment selector, which is in a separate register, so it bypasses the 32-address-line limitation.

2) the segment descriptor contains the 32-bit address of a segment, which is a 32-bit value. Adding the 32-bit offset to it is a simple arithmetic addition, so you end up with a 32-bit address. 2^32=4GB only.

The thing is, the segments may overlap. The mistake in your math is in the fact the index of the current segment descriptor (14 bits) and the offset (32 bits) are not concatenated. They are processed to form a 32-bit linear address.

Check out this page for more information about x86 memory segmentation.

Intel x86 memory model has segmentation and paging. What does it mean that the system can address upto 64 terabytes of virtual memory. My understanding is that only 4GB of virtual memory is addressable. What is the gap here? This is all in the context of 32 bit processor

Here is the math:

2^13 (segments selectors) * 2 (LDT or GDT) * 2^32 = 2^46 = 64 Terabytes. This is referred to in the literature as total virtual memory. Are they wrongly terming it virtual memory? What confuses me is, the processor itself has only 32 bit address lines.

Or, are they trying to say that this is the total virtual memory that can be allocated total (across all processes?)

I think what is being said here that the x86 processor is capable of addressing up to that much memory, not that it does in practice. That would only be possible if the program used the segmented memory model and utilized both a full segment and GP register and the CPU's were wired use them in that way. However, programs today typically use the flat memory model (which can address less memory) and operating systems does not support addressing that much memory AFAIK.

And from §3.3.1 of the manual [1]:

Segmented memory model — [...] Programs running on an IA-32 processor can address up to 16,383 [2¹⁴] segments of different sizes and types, and each segment can be as large as 2³² bytes.

So apparently they are wired to be able to address 2⁴⁶ (64 TiB) bytes of (virtual and physical?) memory but we are confined to what memory model is used in the programs and whether the operating system supports it.

It would actually be usable – you can swap memory to disk and actually address that much virtual memory if need be, so the figures should be correct, and you can call it virtual memory indeed.

However, an x86 processor in 32 bit mode would only be able to address 4 GB at once without swapping, and no system I've heard of ever used that much memory while in 32-bit mode, and it would usually not be very practical due to performance.

1) the segment descriptor is chosen out of these 2^13*2=2^14 by a segment selector, which is in a separate register, so it bypasses the 32-address-line limitation.

2) the segment descriptor contains the 32-bit address of a segment, which is a 32-bit value. Adding the 32-bit offset to it is a simple arithmetic addition, so you end up with a 32-bit address. 2^32=4GB only.

The thing is, the segments may overlap. The mistake in your math is in the fact the index of the current segment descriptor (14 bits) and the offset (32 bits) are not concatenated. They are processed to form a 32-bit linear address.

Check out this page for more information about x86 memory segmentation.

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