Basically , I want to know What an ARM Simulator is ? IS it something like an Assembly language simulator ? If so what are the differences in comparison with Verilog Simulators?
Your question is quite broad/vague. but here goes.
An arm simulator, from the context of what you are asking, is likely an instruction set simulator. Software that just like a processor decodes the instructions, keeps track of the registers, and simulates the execution (if an instruction says add 1 to r1 then you have a variable in software that represents r1 and you add one to it).
A verilog simulator, is not really any different just a different language. verilog is a hardware design language, before you can simulate it you need to compile it. Just like any other high level language it needs to be compiled down to something related to the target. simulators will have their own target logic blocks. The verilog is compiled down to these blocks then that logic is simulated, not unlike the arm simulator. For each clock cycle you update the inputs to each logic element based on the output of the connected block from the prior cycle, then evaluate each logic element and determine the outputs. repeat forever. for each verilog simulator you have a different target at its core, partly why you (can) get different results from each simulator for the same code. Likewise when you compile for the actual target, fpga, asic, etc, it is compiled differently than the simulator (or can be, depends on the environment, simulator, etc).
There is no magic at all to any of these simulators, an instruction set simulator is generally easy to write, a worthwhile task for anyone wanting to get a good strong knowledge of an instruction set or how computers work (start with something small like lc-3, should take less than half an hour). A FAST simulator, that is another story, but a FUNCTIONAL simulator is fairly easy to write. Once compiled to a netlist of simple logic components a verilog simulator is probaby easy as well the biggest task though is the volume of signals and items to evaluate and parsing the code to get at the list of signals and logic functions and who is tied to what. Not as easy as an instruction set simulator, but quite understandable how it works and what the task would be...Verilator is pretty cool as it turns it into lines of C++ code, MANY lines, and a good sized project can take many hours to days to compile even on a screaming machine. (hint turn off waveforms to cut the compile time way down). But the task is understandable when you look at what is going on.
Basically , I want to know What an ARM Simulator is ? IS it something like an Assembly language simulator ? If so what are the differences in comparison with Verilog Simulators?
Your question is quite broad/vague. but here goes.
An arm simulator, from the context of what you are asking, is likely an instruction set simulator. Software that just like a processor decodes the instructions, keeps track of the registers, and simulates the execution (if an instruction says add 1 to r1 then you have a variable in software that represents r1 and you add one to it).
A verilog simulator, is not really any different just a different language. verilog is a hardware design language, before you can simulate it you need to compile it. Just like any other high level language it needs to be compiled down to something related to the target. simulators will have their own target logic blocks. The verilog is compiled down to these blocks then that logic is simulated, not unlike the arm simulator. For each clock cycle you update the inputs to each logic element based on the output of the connected block from the prior cycle, then evaluate each logic element and determine the outputs. repeat forever. for each verilog simulator you have a different target at its core, partly why you (can) get different results from each simulator for the same code. Likewise when you compile for the actual target, fpga, asic, etc, it is compiled differently than the simulator (or can be, depends on the environment, simulator, etc).
There is no magic at all to any of these simulators, an instruction set simulator is generally easy to write, a worthwhile task for anyone wanting to get a good strong knowledge of an instruction set or how computers work (start with something small like lc-3, should take less than half an hour). A FAST simulator, that is another story, but a FUNCTIONAL simulator is fairly easy to write. Once compiled to a netlist of simple logic components a verilog simulator is probaby easy as well the biggest task though is the volume of signals and items to evaluate and parsing the code to get at the list of signals and logic functions and who is tied to what. Not as easy as an instruction set simulator, but quite understandable how it works and what the task would be...Verilator is pretty cool as it turns it into lines of C++ code, MANY lines, and a good sized project can take many hours to days to compile even on a screaming machine. (hint turn off waveforms to cut the compile time way down). But the task is understandable when you look at what is going on.
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